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summary t c901 06f g page 1 rev .100 20 15/09/30 toshiba cmos digital integrated circuit silicon monolithic TC90106FG multi system video decoder for component input TC90106FG is the video decoder which incorporated a v ideo selector. the cvbs supports 3 input, and the component or y/c supports 2 inpu t. the component supports 480i & 480p & 576i & 576p. the output supports itu - r bt.656 or 4 : 2 : 2 signal of 8bits serial output ( sav & eav implantation) 1. feature ? input signal : cvbs is 3ch, s - video is 2 ch, component is 2ch. ? internal 10bit adc 1ch and 8bit adc 2ch. ? y/c separation : 3 - line ycs ( nts c /pal ) b and p ass f ilter ( secam ) ? full multi - color decoder ? picture process y : brightness , contrast , sharpness, noise cancel, v - enhance, lti c : tof, acc, colo r gain, cti, noise cancel , hue ? judg ment of d1/d2 ? function to output high/low on a terminal when not a signal. ? automatically mute function when not a signal. ? f unction to improve gradation. ? 8 bit itu - r bt.656 / 8bit 4 : 2 : 2 serial + sav/eav implantati on + sync output ? i 2 c - bus control ? operating temperature : - 40c to + 85 c ? package : l qfp 64- p - 1010 - 0.50e (0.50 mm pitch) ? power supply : 3.3 v, 2.5 v, 1.5 v lqfp64 -p- 1010- 0.50e weight : 0.4 g (typ . ) ?2015 toshiba corporation
summary t c901 06f g page 2 rev .100 20 15/09/30 2. block diagram the function block / circuit / fixed value in the block diagram omit this , or it easily writes it. 3. pin layout 42 mh z x?tal vertica l 10 bit adc cvbs 2 iic -bus s w ycbcr 1 ycbcr 2 s1 s2
summary t c901 06f g page 3 rev .100 20 15/09/30 4. pin descriptions pin no . pin name pin function pin type withstand voltage [v] processing at unused time 1 avddad3w 2.5 v power supply for adc vdd 2.5 2 avssad3 gnd for adc gnd 0 3 daout output of dac circuit out 2. 5 4 avddpll 2.5 v power supply for dac/pll vdd 2.5 5 vcofil vco filter terminal out 2.5 6 pllin input of pll circuit in 2.5 7 avsspll dac/pll gnd gnd 0 8 avssxo gnd for x'tal circuit gnd 0 9 xtin input for x'tal circuit in 2.5 10 xto ut output for x'tal circuit out 2.5 11 avddxo power supply for x'tal vdd 2.5 12 dvdd1wa 1.5 v power supply for logic circuit vdd 1.5 13 sda i 2 c - bus sda terminal in/out 5.0 14 scl i 2 c - bus scl terminal in 5.0 15 resetn system reset in 3.3 16 dvss1 digital gnd gnd 0 17 data7 data7 output out 3.3 open 18 data6 data6 output out 3.3 open 19 vddio1 3.3 v power supply for i/o vdd 3.3 20 data5 data5 output out 3.3 open 21 data4 data4 output out 3.3 open 22 dvss2 digital gnd gnd 0 23 dvdd2 1.5 v power supply f or logic circuit vdd 1.5 24 data3 data3 output out 3.3 open 25 data2 data2 output out 3.3 open 26 data1 data1 output out 3.3 open 27 data0 data0 output out 3.3 open 28 dvss3 digital gnd gnd 0 29 vddio2 3.3 v power su pply for i/o vdd 3.3 30 clk clock signal output out 3.3 31 vd vd signal output out 3.3 open 32 hd h d signal output out 3.3 open
summary t c901 06f g page 4 rev .100 20 15/09/30 pin n o . pin name pin function pin type withstand voltage [v] processing at unused time 33 fld field signal output out 3.3 open 34 dvss4 digital gnd gnd 0 35 enb enable signal output . it is same the hd timing. out 3.3 open 36 dvdd3 1.5 v power supply for logic circuit vdd 1.5 37 vddio3 3.3 v power supply for i/o vdd 3.3 38 detsig output of no signal low n o signal high in signal out 3.3 open 39 moni0 monitor output terminal 0 out 3.3 open 40 moni1 monitor output terminal 1 out 3.3 open 41 test0 for test signal, connect to gnd in 3.3 42 test1 for test signal, connect to gnd in 3.3 43 slave slave ad dress select in 3.3 44 vddio4 3.3 v power supply for i/o vdd 3.3 45 dvss5 digital gnd gnd 0 46 dvdd4 1.5v power supply f or logic circuit vdd 1.5 47 avddad1 2.5v power supply for adc vdd 2.5 48 avssad1 analog gnd for adc gnd 0 49 cvbs1in cvbs input 1 in 2.5 to gnd via 0.1 50 adbias1 bias terminal for 10bit adc bias 2.5 - 51 cvbs2in cvbs i nput 2 in 2.5 to gnd via 0.1 52 vrt upper limit r eference voltage for adc bias 2.5 53 cvbs3in cvbs i nput 3 in 2.5 to gnd via 0.1 54 vrm m idd le of r eference volt age for adc bias 2.5 - 55 y1in y i n put 1 in 2.5 to gnd via 0.1 56 vrb lower limit r eference volt age for adc bias 2.5 - 57 cb1in cb i n put 1 in 2.5 to gnd via 0.1 58 cr1in cr i n put 1 in 2.5 to gnd via 0.1 59 adbias2 bias ter minal for 8bit adc bias 2.5 - 60 y2in y i n put 2 in 2.5 to gnd via 0.1 61 avddad2 2.5v power supply for adc vdd 2.5 - 62 cb2in cb i n put 2 in 2.5 to gnd via 0.1 63 avssad2 analog gnd for adc gnd 0 - 64 cr2in cr i n put 2 in 2.5 to gnd via 0.1
summary t c901 06f g page 5 rev .100 20 15/09/30 4.1 x'tal input and output terminal terminal 9 and terminal 10 is connection terminal of crystal. the inverter is contained between 9pin and 10pin of the ic. let it oscillate in the basic wave of the crystal oscillator. the following figures are re commended basic wave oscillation circuits. recommended x ? tal is fundamental frequency of 42mhz. the frequency deviation of the crystal oscillator chooses to be small. the frequency deviation influences the subcarrier lock range of f sc . when the deviation of 50 ppm, ntsc is 179 hz (50 ppm of 3.579545 mhz) , pal is 222 hz, it is shifted the center of subcarrier lock range . standard for subcarrier lock range is - 500 hz to + 500 hz in this case, ntsc is - 321 hz ( - 500+179) to + 679 hz (500+179). the subcarrier lock range of fsc is p ossible to change by 16h _ d6 , normal mode( 16h _d 6 = 0 ) : fsc 500 hz wide mode ( 16h _ d6 = 1 ) : fsc 800 hz 4.2 dac output to pllin h pll is composed of 3 pin : dac - out to 5 pin : vco - filter to 6 pin : pll - in it composes as vco - out becomes the h - loc k. the following figures are recommended circuits. 9 10 1 m 330 8 pf 8 pf 5 vco f rom phase det ect lpf dc cut filter 0.01 f 1500 p f 6 6 . 75 mhz 6 . 75 mhz 1 . 5 k
summary t c901 06f g page 6 rev .100 20 15/09/30 4.3 cvbs and y input terminal 4 9 pin : cvbs in 1 , 5 1 pin : cvbs in 2 , 53 pin : cvbs in 3 , 55p in : y in 1 , 60 pin : y in 2 are input terminal . the following figure is recommended circuit . the signal of 0.7 vpp is inputted in each terminal via the c ( 0.47 f ). 5. function 5.1 overview TC90106FG supports cvbs signal and y/c signal(s signal) and component signal ( d1 or d2 ) . the cvbs signal can choose one among three input. the c hosen cvbs is processed by the 3line ycseparation and multi - color decode r . and output is itu - r bt.656 and hd, vd, field. component s ignal supports 480i, 480p, 576i and 576p. the component signal can choose one from two inputs . and output is 54 mhz 8bit ( sav&eav implantation) and hd, vd. it chooses one among this input and can output it. and incorporate various picture improvement functions . 5.2 input signal 5.2.1 recommended input level TC90106FG supports cvbs signal and y/c signal (s signal) and component signal ( d1 or d2 ) . the dynamic range of y - adc is designed avdd 0.4. ( avdd = 2 .5 v ( typ . ) ) please s et the recommended standard input level on 0.7 vp - p in 140ire in ntsc/pal and y signal of 480i/p, 576i/p. 5.2.2 input table input signal format f requency fh[khz] fv[hz] cvbs ntsc 15.75/15.734 60/59.94 pal 15.625 50 y/c ntsc 15.75/15 .734 60/59.94 pal 15.625 50 ycbcr d1 480i 15.75/15.734 60 576i 15.625 50 d2 480p 31.5/31.469 60 576p 31.25 50 49 0.47 f buffer 0.7 vpp
summary t c901 06f g page 7 rev .100 20 15/09/30 5.2.3 input - output table input signal process ing output signal input format fh [khz] sampling c lock [mhz] internal p roces s ing format out put c lock [mhz] 656 8bit hd vd field cvbs ntsc 15.75/15.734 27 4 : 2 : 2 27 pal 15.625 27 4 : 2 : 2 27 y/c ntsc 15.75/15.734 27 4 : 2 : 2 27 pal 15.625 27 4 : 2 : 2 27 ycbcr d1 480i 15.75/15.734 27 4 : 2 : 2 27 576i 15.625 2 7 4 : 2 : 2 27 d2 480p 31.5/31.469 27 4 : 2 : 2 54 - 576p 31.25 27 4 : 2 : 2 54 -
summary t c901 06f g page 8 rev .100 20 15/09/30 5.2.4 typical level of analog input signal 1 ) cvbs signal / y signal cvbs( y ) signal ( to 10bit adc ) has to input 0.7 vp - p (equal 140ire ) at the time of ntsc use. and, the c input at the time of the s - input, 2) a s shown, input level for adc of c is 0.2 vp - p (equal 40ire ) . ( when vdd was 2.5 v, and 140ire of the ntsc signal assumed it 0.7 vp - p. ) when you use it in ycbcr, please be careful abo ut input levels to c - ad (8bit adc). as for the input level of cbcr ( 8 bit adc ) , please make 100% input 0.7 vp - p, like 3) figures. (the figure above is 75% color bar signal) an input and output level list when it was based on 100% input. i nput input level : vp - p ( *1 ) o utpu t : lsb ( *2 ) notes cvbs 0.7 vp - p ( 500 mvp - p ) 16 - 235 ( 8bit ) output is 656 format y 0.7 vp - p ( 500 mvp - p ) 16 - 235 ( 8bit ) output is 656 format c 0.2 vp - p (burst) 31 - 225 ( 8bit ) output is 656 format cb 0.7 vp - p 31 - 225 ( 8 bit ) output is 656 forma t cr 0.7 vp - p 31 - 225 ( 8bit ) output is 656 format *1 input level : input level of cvbs and y is 140ire at white 100%. i n () , it is the level from a pedestal to white 100%. input level of c ( chroma ) is burst level of ntsc - cvbs s ig n al. input level of cbcr is a level at the time of color - 100% signal. *2 output level : output level of cvbs and y is 140ire at white 100% of ntsc. ( output is the level from a pedestal to white 100%. ) outpu t level of c is cbc r output level at time of color - 100% signal. output of cbcr is a input at the time of color - 100% signal. (note s ) mentioned output level chang es by picture level adjustment of contrast, gain, acc, etc. these are not maximum level. 100 -40 0 20 40 60 80 -20 256 51 767 0 1023 avdd0.4v 0.7vp-p
summary t c901 06f g page 9 rev .100 20 15/09/30 2) c signal 3) cb/c r signal 103 0 255 153 128 0 20 -20 ire
summary t c901 06f g page 10 rev .100 20 15/09/30 5.3 signal output 5.3.1 hv snc proces s this ic processes horizontal sync separation and vertical sync separation, and outputs a signal of hd and vd. there are two output mode for pulse p hase and puls e width. o ne is based on 656 format, other one is sync through mode which can output same timing and width as sync of input signal. in 656 format mode, it is selectable from 656 - 3 and 656 - 4 mode. se tting the 656 mode ntsc ( cvbs) vbit : 1 vbit : 0 fbit : 1 fbit : 0 9 line sav 9 line eav 3 line sav 656-3 263 line sav 3 line eav 263 line eav 272 line sav 265 line sav 272 line eav 265 line eav 525 line sav 525 line eav 528 (3) line sav 528 (3) line eav 19 line sav 19 line eav 3 line sav 656-4 263 line sav 3 line eav 263 line eav 282 line sav 265 line sav 282 line eav 265 line eav 525 line sav 525 line eav 528(3) line sav 528 line eav
summary t c901 06f g page 11 rev .100 20 15/09/30 5.3.2 656 output timing of 480i / 60hz ntsc(525line/60hz) second field(even) 266 267 2 75 263 262 261 270 271 272 273 274 ntsc (525 line/60 hz) first field (odd) at (25h_d6 : 0, 29h_d4 : 0) 3 2 1 525 524 523 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 output hd vd field field2 field1 s av 28 0 277 field at (25h_d6 : 1, 29h_d4 : 1) e av e av s av at (25h_d6 : 0, 29h_d4 : 0) 26 4 26 5 28 4 28 5 28 6 a t (25h_d6 : 1, 29h_d4 : 1) output e av s av field2 e av s av vbit fbit vd vd hd hd field hd vd field 26 8 26 9 2 76 2 78 2 79 2 81 2 82 2 83
summary t c901 06f g page 12 rev .100 20 15/09/30 5.3.3 output format output is 656 (27mhz_8bit_eav&sav) when input signal is cvbs, s, ycbcr (d1) . output is 54 mhz_8bit_ seria l_ eav&sav when input signal is ycbcr ( 525p/625p). y: pedestal level = 16 lsb c : center electric potential = 128 lsb signal process of y output signal below pedestal is set by register clp (bank 0, sub address 29h). clp = 1 : the signal under pedestal le vel is fixed on 16lsb clp = 0 : the signal under pedestal level is outputted through output bit data rate notes y cbcr [0 - 7] 8 27mhz ? 54mh z itu - r bt.656 field 1 - - clk 1 27mhz ? 54mhz - hd 1 f h separated h orizontal sync vd 1 f v separated v ertical sync
summary t c901 06f g page 13 rev .100 20 15/09/30 6. absolute maximum rating the maximum ratings are rated values which must not be exceeded during oper ation, even for an instant. exceeding the maximum rating may result in destruction, degradation or other damage to the ic and other components. when designing applications for this ic, be sure that none of the maximum rating values will ever be exceeded. characteristics symbol rating unit power voltage1 (1.5v system) vdd1 - 0.3 to vss+2.0 v power voltage2 (2.5v system) vdd2 - 0.3 to vss+3.5 v power voltage3 (3.3v system) vdd3 - 0.3 to vss+3.9 v input voltage (2.5v system) vin2 - 0.3 to vdd+0.3 v inpu t voltage (3.3v system) vin3 - 0.3 to vdd+0.3 v input voltage (3.3v system, 5v withstand voltage) vin4 ( note1 ) - 0.3 to vss+5.5 v potential difference between power pins (between 1.5 v system power pins) vdg1 ( note2 ) 0.3 v potential difference between power pins (between 2.5 v system power pins) vdg2 ( note3 ) 0.3 v potential difference between power pins (between 3.3 v system power pins) vdg3 ( note4 ) 0.3 v power dissipation pd ( note5 ) 1667 mw storage temperature tstg - 40 to 125 c note1 : the wi thstand voltage for pins (sda, scl) is 5 v. note2 : when you supply a voltage to the vdd pin of 1.5 v of voltage , the potential difference between these vdd pin , please do not exceed the rated value of the described . note3 : when you supply a voltage to t he vdd pin of 2.5 v of voltage , the potential difference between these vdd pin please do not exceed the rated value of the described . note4 : when you supply a voltage to the vdd pin of 3.3 v of voltage , the potential difference between these vdd pin ple ase do not exceed the rated value of the described . and, keep the maximum potential difference between all vss pins within 0.01 v. note5 : if you intended to use a temperature higher than ta = 25c, reduce by 16.67 mw per one degree (c) increase. 2000 1000 0 1667 667 0 0 1000 2000 0 25 50 75 100 125 S?p? [mw] ?? ta lqfp64 - p - 1010 - 0.50e S?p? power dissipation characteristics ambient temperature ta [ c ] 1000 2 000 power dissipation [mw]
summary t c901 06f g page 14 rev .100 20 15/09/30 7. operating condition the TC90106FG is not guaranteed to function correctly if it is used outside its specified power voltage rage (1.5 v system power : 1.40 v to 1.60 v, 2.5 v system power : 2.3 v to 2.7 v, 3.3 v system power : 3.0 v to 3.6 v). pleas e use within the specified operating conditions. if you temporarily lea ve and then return to the specified operating conditions, this ic?s conditions will change, and so it is necessary to reset the ic?s power to continue using it correctly within the spec ified operating conditions. characteristics corresponding terminal symbol min typ. max unit power voltage of digital block 12, 23, 36, 46 vdd - d 1.4 1.5 1.6 v power voltage of i/o block 19, 29, 37, 44 vdd - io 3.0 3.3 3.6 v power voltage of xo block 11 vddxo 2.3 2.5 2.7 v power voltage of pll block 4 vddpll 2.3 2.5 2.7 v power voltage of analog block 1, 47, 61 vddda, vddad 2.3 2.5 2.7 v operating templature - topr - 40 85 c
summary t c901 06f g page 15 rev .100 20 15/09/30 8. electrical characteristic 8.1 dc characteristic ta = 25c , vdd1 = 1 .50 0.1 v, vdd2 = 2.50 0.2 v, vdd3 = 3.30 0.3 v) charac teristic terminal no. symbol m in t yp . m ax unit notes powers upply current 12, 23, 36, 46 idd1 (1.5 v sys tem ) 30 45 ma 3.3 v system current will change by i/o. 1, 4, 11, 47, 61 idd2 (2.5 v sy s tem ) 100 120 ma 19, 29, 37, 44, idd3 (3.3 v sys tem ) 25 65 ma input voltage 15, 41, 42, 43 vih vdd 3 x 0.8 vdd 3 v 3.3 v i/o terminal 13, 14 5.0 v withstand voltage i/o terminal 15, 41, 42, 43 vil vss vdd 3 x 0.2 v 3.3 v i/o terminal 1 3, 14 5.0 v withstand voltage i/o terminal input current 15, 41, 42, 43 iih - 10 10 a 3.3 v i/o terminal 13, 14 5.0 v withstand voltage i/o terminal 15, 41, 42, 43 iil - 10 10 a 3.3 v i /o terminal 13, 14 5.0 v withstand voltage i/ o terminal o utput voltage 17, 18, 20, 21, 24, 25, 26, 27, 30, 31, 32, 33, 35, 38, 39, 40 v oh vdd3 - 0.6 ? vdd3 v 3.3 v i/o terminal when 4 ma out load v ol vss ? 0.4 v 3.3 v i/o terminal when 4 ma out load
summary t c901 06f g page 16 rev .100 20 15/09/30 9. pack a ge lqfp64 - p - 1010 - 0.5 0 e unit : mm weight : 0.4 g ( typ .)
summary t c901 06f g page 17 rev .100 20 15/09/30 10. revision history date revision contents 1 5 /0 9 / 30 1 . 0 0 first edition
summary t c901 06f g page 18 rev .100 20 15/09/30 restrictions on product use ? toshiba corporation, and its subsidiaries and affiliates (collectively "toshiba"), reserve the right to make changes to the i nformation in this document, and related hardware, software and systems (collectively "product") wi thout notice. ? this document and any information herein may not be reproduced without prior written permission from toshiba. even with toshi ba's written permission, reproduction is permissible only if reproduction is without alteration/omission. ? though toshiba works continually to improve product's quality and reliability, product can malfunction or fail. customers are respon sible for complying with safety standards and for providing adequate designs and safeguards for their hardware, software and system s which minimize risk and avoid situations in which a malfunction or failure of product could cause loss of human life, bodily injury or damage to property, including data loss or corruption. before customers use the product, create designs including the p roduct, or incorporate the product into their own applications, customers must also refer to and comply with (a) the latest versions of all relevant tos hiba information, including without limitation, this document, the specifications, the data sheets and a pplication notes for product and the precautions and conditions set forth in the "toshiba semiconductor reliability handbook" and (b) the instructions for the app lication with which the product will be used with or for. customers are solely responsible for all aspects of their own product design or applications, including but not limited to (a) determining the appropriateness of the use of this product in such design or applications; ( b) evaluating and determining the applicability of any information co ntained in this document, or in charts, diagrams, programs, algorithms, sample application circuits, or any other referenced documents; and (c) validating all operating parameters for such designs and app lications. toshiba assumes no liability for customer s' product design or applications. ? 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